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Computer Networking Research Laboratory

Dept. of Electrical & Computer Engineering, Colorado State University

Testing and Testable Design of ICs

Introduction

The testing of complex VLSI circuits poses many technical challenges. This project is aimed at enhancing all aspects of testing of ICs including test generation, fault coverage and design for testability. Recent results include CMOS, BiCMOS and ECL logic gate design techniques for enhanced testability, resolution enhancement of IDDQ testing,  the design of sensors for IDDQ testing, and design of IDDQ test able random access memories.  Present research involves test generation for IDDQ testing, use of IDDQ testing for submicron designs, as well as the use of antirandom tests for combinational and sequential circuits.
This project is done in collaboration with Prof. Y. K. Malaiya in the Computer Science Department at the Colorado State University.

Team members

  Alumni

  • Rochit Rajsuman
  • Waleed Al-Assadi
  • Sankaran Menon
  • Umesh Metha
  • Sri Jandhyala
  • Shenhui Wu
  • Arun Palinaswami
  • Ashwin K. Rao
  • Ruyi Fan
  • Ritesh Turakhia
  • Chinmay Gupte
  • Ashish Banthia
  • Priyanka Dumbre
  • Ashutosh Sharma
  • Prasanna Manja Ramakrishna
  • Supriya Sukumaran
  • Kasturi Ghosh

Publications

  1. S. M. Menon, A. P. Jayasumana, and Y. K. Malaiya, "Manifestation of Faults in Single- and Double-BJT BICMOS Logic Gates," Proceedings of IEE, Part E: Computers and Digital Techniques, vol. 142, No. 2, March 1995, pp. 135-44.
  2. K. Mody and A. P. Jayasumana, "An Efficient Multi-Layer Diagonal Router for Printed Circuit Boards," Computers and Electrical Engineering - An International Journal, vol. 21, No. 3, May 1995, pp. 147-58. (Available from ScienceDirect)
  3. S. M. Menon, Y. K. Malaiya, A. P. Jayasumana, and R. Rajsuman, "Testable Design of BiCMOS Circuits for Stuck-Open Fault Detection using Single Patterns," IEEE Journal of Solid State Circuits, vol. 30, No. 8, Aug. 1995, 855-63.
  4. S.M. Menon, A.P. Jayasumana, and Y.K. Malaiya, "A Novel High-Speed BiCMOS Domino Logic Family," Proc. IEEE International Symposium on Circuits and Systems (ISCAS), April 1995, pp. 21-24.
  5. W. A. Al-Assadi, A.P. Jayasumana, and Y.K. Malaiya, "A Bipartite Differential IDDQ Testable Static RAM Design," Proc. IEEE International Workshop on Memory Technology, Design and Testing, Aug 1995, pp. 36-45.
  6. W. A. Al-Assadi, A.P. Jayasumana, and Y.K. Malaiya, "A Bipartite, Differential, IDDQ Testable Static RAM Design," Proc. IEEE International Workshop on IDDQ Testing (IDDQ'95), Oct. 1995, pp. 54-59.
  7. S. Menon, A. P. Jayasumana, and Y. K. Malaiya, "Input Pattern Classification for Transistor Level Testing of Bridging Faults in BiCMOS Circuits," Proc. Great Lakes Symposium on VLSI, March 1996.
  8. S.M. Menon, Y.K. Malaiya, and A.P. Jayasumana, "Input Pattern Classification for Detection of Stuck-on and Bridging Faults Using IDDQ Testing in BiCMOS and CMOS Circuits," Proc. IEEE International Conference on VLSI Design, Jan. 1997.
  9. W. K. Al-Assadi, A. P. Jayasumana, and Y. K. Malaiya, "IDDQ Testable Static RAM Design," Proceedings of the NASA Symposium on VLSI Design, March 1997.
  10. S. M. Menon, Y. K. Malaiya, A. P. Jayasumana, and Q. Tong, "Operational and Test Performance in the Presence of Built-in Current Sensors," Journal of VLSI Design, vol. 5, No. 3, pp. 285-98, 1997.
  11. S. Menon, A. P. Jayasumana, and Y. K. Malaiya, "ECL Storage Elements: Modeling of Faulty Behavior," IEEE Transactions on Circuits Systems-II: Analog and Digital Signal Processing, vol.44, No. 11, pp. 970-974, November 1997.
  12. S. Menon, A. P. Jayasumana, and Y. K. Malaiya, "BiCMOS Domino: A Novel High-Speed Dynamic BiCMOS Logic," International Journal of Electronics, vol. 83, No. 2, pp 177-89, 1997.
  13.  S. Wu, Y.K. Malaiya, and A.P. Jayasumana, "Antirandom vs. Pseudorandom Testing," Proc. IEEE Int. Conf. on Computer Design, Oct. 1998, pp. 221-3.
  14. S. Jandhyala, H. Balachandran, S. Menon, and A. Jayasumana, "Clustering Based Identification of Faulty ICs Using IDDQ Tests," Proc. 1998 IEEE International Workshop on IDDQ Testing, Oct. 1998.
  15. S. Jandhyala, H. Balachandran, and A. Jayasumana, "Clustering Based Techniques for IDDQ Testing," Proc. International Test Conference, Sept. 1999.
  16. A. Palaniswami, A. Jayasumana, and Y. K. Malaiya, "A Neural Network Based Approach for Testing Analog Circuits with Frequency Domain Classification and Time Domain Testing," Proc. IEEE System Test and Diagnosis Workshop, Sept. 1999.
  17. S. Jandhyala, H. Balachandran, and A. Jayasumana, ``Reducing Dependence on Arbitrary Thresholds with IDDQ Testing,'' TI Technical Journal, Texas Instruments, Oct.- Dec. 1999.
  18. S. Jandhyala, H. Balachandran, M. Sengupta, and A. Jayasumana,  "Clustering Based Evaluation of IDDQ Measurements: Applications in Testing and Classification of ICs,'' Proc. IEEE VLSI Test Symposium, Montreal, Canada, pp. 444-449, April 2000.
  19. A. Rao, A.P. Jayasumana, and Y.K. Malaiya, "Optimal Clustering and Statistical Identification of Defective ICs using IDDQ Testing," Proc.  IEEE International Workshop on Defect Based Testing (DBT 2000), Montreal, Canada, April 2000.
  20. Xueping Jiang, A. P. Jayasumana, W. Zhang, and S. Chiao, "A Proper Deep Submicron MOSFET Model (PDSMM) and Its Applications for Delay Modeling of CMOS Inverters," Proc. Sixth International Conference on Solid-State and Integrated-Circuit Technology (ICSICT2001), Shanghai, China,  Vol. 2, 875-878, October, 2001.
  21. R. Turakhia, A. P. Jayasumana, and Y. K. Malaiya, "Clustering-Based Production-Line Binning of ICs Based on IDDQ," Proc. IEEE International Workshop on Defect Based Testing (CDBT 2003), Nappa Valley, CA, pp. 65-73, April 2003.
  22. X. Jiang and A. P. Jayasumana, "Input Collapse of CMOS Logic Gates with a Series-Connected MOSFET Chain," Proc. 7th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT2004), Beijing, China, October, 2004.
  23. A. S. Banthia, A. P. Jayasumana, and Y.K. Malaiya, "Data Size Reduction for Clustering-Based Binning of ICs using Principal Component Analysis,"  Proc.  IEEE International Workshop on Defect Based Testing (DBT 2005),  CA, May 2005.
  24. A. Sharma, A.P. Jayasumana, and Y. K. Malaiya, "X-IDDQ: A Novel Defect Detection Technique using IDDQ Data," Proc. 24th IEEE VLSI Test Symposium, Berkeley,  CA, April 2006.
  25. S. Wu, S. Jandhyala, Y. K. Malaiya, and A. P. Jayasumana "Antirandom Testing: A Distance Based Approach," VLSI Design. Vol. 2008 (2008), Article ID 165709, 9 pages, doi:10.1155/2008/165709
  26. X. He, Y. Malaiya, A. P. Jayasumana, K. P. Parker, and S. Hird, "Outlier Detection in Capacitive Open Test Data Using Principal Component Analysis," Presented at the IEEE 8th International Board Test Workshop (BTW'09), Fort Collins, CO, Sept. 2009.
  27. X. He, Y. K.  Malaiya, A. P. Jayasumana, K. P. Parker, and S. Hird, "An Outlier Detection Based Approach for PCB Testing," In Proc. 40th International Test Conference (ITC09), Austin, Texas, November 2009.

Posters

  1. Xin He, Yashwant Malaiya, Anura Jayasumana, and Kenneth Parker, "An Outlier Detection Based Approach for PCB Testing," Agilent University Research Fair, Loveland, CO, Feb. 2009.